FIG. 18 shows a conventional pulse width modulation (PWM) circuit 1800 that includes a counter circuit 1802, a comparator 1804, reset logic 1806, a period register 1808, and a pulse width register 1810.
In operation, a counter circuit 1802 can increment a “Count” output value in response an input clock signal CLK. While a count value (Count) is less than a “Width” value provided by pulse width register 1810, a comparator 1804 may drive output signal PWM_OUT to one level (e.g., high or low). However, when the count value (Count) exceeds value Width, comparator 1804 can drive output signal PWM_OUT to the other level (e.g., low or high).
Once a terminal count value is reached, a terminal count output (TC) can be activated, and a count value within counter circuit 1802 can be reset to a start value (less than Width) through reset logic 1806. The process can then repeat for a next PWM_OUT cycle. A period register 1808 can provide the terminal count value, and thus establish period of output signal PWM_OUT,
FIG. 19 is a timing diagram showing the operation of conventional PWM circuit like that of FIG. 18. FIG. 19 includes a waveform for an input clock signal (CLK) as well as three different examples of output signal PWM_OUT corresponding to different Width values (i.e., Width=3, 4, 2). FIG. 19 shows how a pulse width of an output signal PWM_OUT can be varied by a Width value. However, the resolution of pulse width changes is limited to increments of TCLK, where TCLK is the period of input clock signal (CLK). To increase a pulse width resolution in the conventional system, a frequency of input clock (CLK) is increased.